Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
نویسندگان
چکیده
منابع مشابه
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By taking the test strategy into account during the synthesis of the circuit, the overhead due to the test features can be reduced. We present a synthesis-for-scan procedure, called beneficial scan, that orders the scan ch...
متن کاملATPG for scan chain latches and flip-flops
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by m...
متن کاملTwo-dimensional test data compression for scan-based deterministic BIST
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, determin...
متن کاملModeling Scan Chain Modifications For Scan-in Test Power Minimization
Rapid and reliable test of SOCs necessitates upfront consideration of the test power issues. Special attention should be paid to scanbased cores as the test power problem is more severe due to excessive switching activity stemming from scan chain transitions during shift operations. We propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain thr...
متن کاملEfficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
FPGAs are attractive devices due to their low development cost and short time-to-market, and widely used not only for reconfigurable purpose but also as applicationdependent embedded devices for low-volume products. This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. In order to build up BIST components such as LFSR, MISR and scan...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Transactions on Information and Systems
سال: 2010
ISSN: 0916-8532,1745-1361
DOI: 10.1587/transinf.e93.d.10